SYSCTL_RSCLKCFG_PLLSRC=SYSCTL_RSCLKCFG_PLLSRC_PIOSC, SYSCTL_RSCLKCFG_OSCSRC=SYSCTL_RSCLKCFG_OSCSRC_PIOSC
Run and Sleep Mode Configuration Register
| SYSCTL_RSCLKCFG_PSYSDIV | PLL System Clock Divisor |
| SYSCTL_RSCLKCFG_OSYSDIV | Oscillator System Clock Divisor |
| SYSCTL_RSCLKCFG_OSCSRC | Oscillator Source 0 (SYSCTL_RSCLKCFG_OSCSRC_PIOSC): PIOSC is oscillator source 2 (SYSCTL_RSCLKCFG_OSCSRC_LFIOSC): LFIOSC is oscillator source 3 (SYSCTL_RSCLKCFG_OSCSRC_MOSC): MOSC is oscillator source 4 (SYSCTL_RSCLKCFG_OSCSRC_RTC): Hibernation Module RTC Oscillator (RTCOSC) |
| SYSCTL_RSCLKCFG_PLLSRC | PLL Source 0 (SYSCTL_RSCLKCFG_PLLSRC_PIOSC): PIOSC is PLL input clock source 3 (SYSCTL_RSCLKCFG_PLLSRC_MOSC): MOSC is the PLL input clock source |
| SYSCTL_RSCLKCFG_USEPLL | Use PLL |
| SYSCTL_RSCLKCFG_ACG | Auto Clock Gating |
| SYSCTL_RSCLKCFG_NEWFREQ | New PLLFREQ Accept |
| SYSCTL_RSCLKCFG_MEMTIMU | Memory Timing Register Update |